1. Field of the invention
The present invention relates to integrated circuits fabrication techniques and in particular to a technique for making trench isolation structures encased in a semiconducting substrate.
2. Description of the prior art
Compared with customary isolation structures made by thermally growing a thick field oxide layer over silicon areas defined by a silicon nitride mask, trench isolation structures (commonly known as BOX structures; an acronym for Buried OXide) offer potentially great advantages in terms of greater compactness and utilization of substantially "cold" processes for making them. Basically the encased trench isolation structure is made by pre-excavating the semiconductor substrate (monocrystalline silicon) and filling the trench with a dielectric material (generally a low-temperature chemically deposited silicon oxide) which advantageously may be planarized by any known technique.
Of course the walls of the trench formed in the semiconductor substrate for making the BOX isolation structure may be implanted customarily with a dopant in order to increase the doping level of the semiconductor material adjacent to the encased dielectric material.
The compactness requirement imposes very strict dimensional tolerances and excavating trenches among adjacent active areas on the front of the semiconductor device is problematic. The use of an intrinsically anisotropic RIE technique for the trench, though allowing a precise dimensional control of the etching performed through a photo-resist mask, produces a trench having excessively steep, substantially vertical, walls which are difficult to be implanted without recurring to special implantation techniques. Moreover the rather acute bottom corners of the etched trench may cause dangerous discontinuity effects in the electric field induced within the semiconductor substrate.
In order to overcome these drawbacks, recourse to a conventional isotropic plasma etching through a photoresist mask has been proposed for exploiting the under-cut effect of the isotropic etching in order to obtain an etching profile with a rounded bottom and inclined lateral walls, more easily implantable after removing the residual photoresist mask. Beyond a certain level of compactness of the integrated structures, this latter method is unusable. In fact, in order to compensate for the loss of lateral dimensional control due to the under-cutting, which may be considered equal to the etch depth, the use of masks having aperture widths below the resolution limit of many presently used photolithographic apparatuses would be necessary. For example, in case of a 4Mbit device with a 2.2 .mu.m pitch (active area: 0.8 .mu.m; isolation: 1.2 .mu.m), for a lateral under-cut of 0.5 .mu.m each side, apertures of 0.4 .mu.m should be photolithographically defined through the photoresist mask.